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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14415 Quad Precision Timer/Driver MC14415 quad timer/driver is constructed with complementary MOS enhancement mode devices. The output pulse width of each digital timer is a function of the input clock frequency. Once the proper input sequence is detected the output buffer is set (turned on), and after 100 clock pulses are counted, the output buffer is reset (turned off). The MC14415 was designed specifically for application in high speed line printers to provide the critical timing of the hammer drivers, but may be used in many applications requiring precision pulse widths. * * * * * * Four Precision Digital Time Delays Schmitt Trigger Clock Conditioning NPN Bipolar Output Drivers Timing Disable Capability Using Inhibit Output Positive or Negative Edge Strobing on the Inputs Synchronous Polynomial Counters Used for Delay Counting L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION MC14415FP (3.0 V-18 V) MC14415VP (3.0 V-6.0 V) MC14415FL (3.0 V-18 V) MC14415VL (3.0 V-6.0 V) MC14415DW (3.0 V-18 V) Plastic Plastic Ceramic Ceramic SOIC IIIIIIIIIIIIIIIIIIIII I II III I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II III I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII IIIIIIII I I II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I II MAXIMUM RATINGS* (Voltages Referenced to VSS) Rating Symbol VDD DC Supply Voltage MC14415FL, FP,DW MC14415VL, VP Value Unit V V - 0.5 to + 18.0 - 0.5 to + 6.0 Input or Output Voltage (DC or Transient) Input Current (DC or Transient), per Pin Vin, Vout Iin - 0.5 to VDD + 0.5 10 20 500 mA mA Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Iout PD mW Tstg TL - 65 to + 150 260 TA = - 55 to 125C for all packages. PIN ASSIGNMENT CLOCK SET SET A SET B SET C SET D ST 1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD INH OUT A OUT B OUT C OUT D DIS ST2 _C _C Lead Temperature (8-Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C BLOCK DIAGRAM SET A 3 SET B 4 SET C 5 SET D 6 14 OUTPUT A INPUT LOGIC DIVIDE-BY- 100 COUNTERS OUTPUT BUFFERS 13 OUTPUT B 12 OUTPUT C 11 OUTPUT D VSS STROBE 2 9 STROBE 1 7 INPUT DISABLE 10 OUTPUT SET 2 CLOCK 1 OUTPUT INHIBIT 15 COMMON LOGIC CLOCK CONDITIONING CIRCUIT VDD = PIN 16 VSS = PIN 8 REV 3 1/94 (c)MC14415 1995 Motorola, Inc. 290 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I I I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I I I I II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III I I I I I I I I I I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I III IIII I III IIIIIIIIIIIIIIIII II II II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II II III I IIIII IIIIII IIII I I I II II II III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Power Dissipation** (Dynamic plus Quiescent) (CL = 15 pF) Quiescent Dissipation Input Capacitance (Vin = 0) Input Leakage Current Output Drive Current (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Output Drive Voltage (NPN Driver) (IOH = 0 mA) Source (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) Noise Immunity (Vout 1.5 Vdc) (Vout 3.0 Vdc) (Vout 4.5 Vdc) Output Voltage (No Load) MOTOROLA CMOS LOGIC DATA (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) v v v (Vout v 1.5 Vdc) (Vout v 3.0 Vdc) (Vout v 4.5 Vdc) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Characteristic "1" Level "0" Level Sink Symbol VOH VOH VNH VOL VNL IOL Cin PQ PD Iin VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 15 10 -- 0.23 0.60 -- Min 1.4 2.9 -- 1.5 3.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.3 0.25 1.0 -- 0.01 0.01 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PD (56 mW/MHz) f + PQ PD (225 mW/MHz) f + PQ PD (510 mW/MHz) f + PQ Min 0.2 0.5 -- 8.0 7.7 7.5 7.1 3.0 2.7 2.5 2.2 1.5 3.0 -- 1.5 3.0 -- 3.0 8.0 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.00001 0.00005 0.00022 0.00050 Typ # 4.14 9.09 14.12 14.12 13.81 13.70 13.61 25_C 0.78 2.0 7.8 9.09 8.45 8.30 8.14 4.14 3.44 3.30 3.08 2.25 4.50 6.75 2.25 4.50 6.75 5.0 0 0 -- 0.3 0.25 1.0 -- 0.01 0.01 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.16 0.40 -- Min 1.5 3.0 -- 1.4 2.9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 -- Max 3.5 14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MC14415 291 mAdc Adc Unit mW mW Vdc Vdc Vdc Vdc Vdc Vdc Vdc pF IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II III I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. SWITCHING CHARACTERISTICS* (CL = 15 pF, TA = 25_C) Clock Input Rise and Fall Times (Figure 1) Input Clock Frequency Input Pulse Width (Figure 1) Input Pulse Coincidence (Figure 3) Turn-Off Delay Time (Inhibit to Output) Turn-On Delay Time (Inhibit to Output) Turn-On Delay Time tPHL = (2.4 ns/pF) CL + 564 ns tPHL = (1.0 ns/pF) CL + 285 ns tPHL = (0.75 ns/pF) CL + 289 ns Turn-Off Delay Time tPLH = (2.7 ns/pF) CL + 560 ns tPLH = (1.2 ns/pF) CL + 282 ns tPLH = (0.91 ns/pF) CL + 286 ns Output Fall Time tTHL = (1.5 ns/pF) CL + 47 ns tTHL = (0.75 ns/pF) CL + 24 ns tTHL = (0.55 ns/pF) CL + 17 ns Output Rise Time tTLH = (2.0 ns/pF) CL + 10 ns tTLH = (1.25 ns/pF) CL + 6 ns tTLH = (1.10 ns/pF) CL + 3 ns MC14415 292 Characteristic OUTPUT CLOCK OUTPUT INPUT 20 ns tPLH tTLH 1 10% tTLH, tTHL 50% Symbol PCmin tPLH tPHL tPHL tPLH tTHL tTLH tWH 2 tWH 90% fcl 90% tTHL 10% tPHL 100 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 50% 50% 20 ns VDD VOL VOH VSS VOH VOL VDD VSS Min 500 450 -- 500 450 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Figure 1. Switching Characteristics -- Waveform Relationships MOTOROLA CMOS LOGIC DATA Typ # 450 350 -- 450 350 -- 300 225 110 300 225 110 600 300 150 600 300 150 0.7 1.0 1.5 70 35 25 40 25 20 -- -- -- 1200 600 -- 1200 600 -- Max 550 425 -- 550 425 -- 150 80 -- 15 5.0 4.0 85 60 -- -- -- -- -- -- -- -- -- -- MHz Unit s ns ns ns ns ns ns ns ns INPUT DISABLE STROBE 2 STROBE 1 SET A OUTPUT SET OUTPUT INHIBIT CLOCK OUTPUT A 1 50% tPLH tPHL 2 100 50% MINIMUM COINCIDENCE = 500 ns @ VDD = 4.75 Vdc 50% INPUT DISABLE STROBE 2 STROBE 1 SET A OUTPUT SET OUTPUT INHIBIT CLOCK OUTPUT A tPLH 1 50% tPHL 2 100 50% MINIMUM COINCIDENCE = 500 ns @ VDD = 4.75 Vdc Mode 1: OUTPUT SET Initiates Time Delay Mode 2: Set A Initiates Time Delay INPUT DISABLE STROBE 2 STROBE 1 SET A OUTPUT SET OUTPUT INHIBIT CLOCK OUTPUT A tPLH 50% tPHL tPLH tPHL 1 50% 2 100 50% INPUT DISABLE STROBE 2 STROBE 1 SET A OUTPUT SET CLOCK OUTPUT A 50% tPLH tPHL 1 100 50% MINIMUM COINCIDENCE = 500 ns @ VDD = 4.75 Vdc Mode 3: OUTPUT INHIBIT Disables Time Delay Mode 4: Positive-Edge Strobe (ST2) Initiates Time Delay Figure 2. Typical Operation Modes and Functional Timing Diagram MOTOROLA CMOS LOGIC DATA MC14415 293 MC14415 294 C2 S Q R SET A 3 C1 VDD DIVIDE-BY-100 SYNCHRONOUS COUNTER ENABLE C2 S Q R SET B 4 DIVIDE-BY-100 C1 SYNCHRONOUS COUNTER ENABLE VSS VDD C2 S Q R SET C 5 DIVIDE-BY-100 C1 SYNCHRONOUS COUNTER ENABLE VSS VDD C2 S Q R SET D 6 C1 DIVIDE-BY-100 SYNCHRONOUS COUNTER ENABLE VSS VDD OUTPUT SET 2 STROBE 2 9 STROBE 1 7 C2 VSS SCHMITT CLOCK CONDITIONING CIRCUIT C1 CLOCK 1 15 OUTPUT INHIBIT 14 OUTPUT A 13 OUTPUT B LOGIC DIAGRAM 12 OUTPUT C 11 OUTPUT D MOTOROLA CMOS LOGIC DATA INPUT DISABLE 10 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 -B- 1 8 C L -T- SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M MOTOROLA CMOS LOGIC DATA MC14415 295 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 -B- 1 8 8X P 0.010 (0.25) M B M 16X D M J TA S 0.010 (0.25) B S F R X 45 _ C -T- 14X DIM A B C D F G J K M P R G K SEATING PLANE M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14415 296 *MC14415/D* MOTOROLA CMOS LOGIC DATA MC14415/D |
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